Overview
The family of LMK0482x devices are verify flexible to meet many application requirements. The typical use case for LMK0482x is as a cascaded dual loop jitter cleaner for JESD204B systems. However traditional (nonJESD204B) systems are possible with use of the large SYSREF divider to produce a low frequency. Note that while the Device Clock outputs (DCLKoutX) do not provide LVCMOS outputs, the OSCout may be used to provide LVCMOS outputs at DCLKout6 or DCLKout8 frequency using the feedback mux.
In addition to dual loop operation, by powering down various blocks the LMK0482x may be configured for single loop or clock distribution modes also.
Jitter Cleaning
The dual loop PLL architecture of the LMK0482x family provides the lowest jitter performance over a wide range
of output frequencies and phase noise integration bandwidths. The first stage PLL (PLL1) is driven by an external
reference clock and uses an external VCXO or tunable crystal to provide a frequency accurate, low phase noise
reference clock for the second stage frequency multiplication PLL (PLL2).
PLL1 typically uses a narrow loop bandwidth (typically 10 Hz to 200 Hz) to retain the frequency accuracy of the
reference clock input signal while at the same time suppressing the higher offset frequency phase noise that the
reference clock may have accumulated along its path or from other circuits. This “cleaned” reference clock
provides the reference input to PLL2.
The low phase noise reference provided to PLL2 allows PLL2 to operate with a wide loop bandwidth (typically 50
kHz to 200 kHz). The loop bandwidth for PLL2 is chosen to take advantage of the superior high offset frequency
phase noise profile of the internal VCO and the good low offset frequency phase noise of the reference VCXO or
tunable crystal.
Ultra low jitter is achieved by allowing the external VCXO or Crystal’s phase noise to dominate the final output
phase noise at low offset frequencies and the internal VCO’s phase noise to dominate the final output phase
noise at high offset frequencies. This results in best overall phase noise and jitter performance.
JEDEC JESD204B Support
The LMK0482x family provides support for JEDEC JESD204B. The LMK0482x will clock up to 7 JESD204B
targets using 7 device clocks (DCLKoutX) and 7 SYSREF clocks (SDCLKoutY). Each device clock is grouped
with a SYSREF clock.
It is also possible to re-program SYSREF clocks to behave as extra device clocks for applications which have
non-JESD204B clock requirements.
Three PLL1 Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*, and CLKin2/CLKin2*)
The LMK0482x family has up to three reference clock inputs for PLL1. They are CLKin0, CLKin1, and CLKin2.
The active clock is chosen based on CLKin_SEL_MODE. Automatic or manual switching can occur between the
inputs.
CLKin0, CLKin1, and CLKin2 each have their own PLL1 R dividers.
CLKin1 is shared for use as an external 0-delay feedback (FBCLKin), or for use with an external VCO (Fin).
CLKin2 is shared for use as OSCout. To use powerdown OSCout, see VCO_MUX, OSCout_MUX,
OSCout_FMT .
Fast manual switching between reference clocks is possible with a external pins CLKin_SEL0 and CLKin_SEL1.